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xilinx_ise_9.x
- 《xilinx_ise_9.x_fpga_cpld设计指南》，光盘源文件- Xilinx_ise_9.x_fpga_cpld Design Guide, the source file CD-ROM
MiNiVOS
- Xilinx ISE&EDK 8.2平台的嵌入式MiNiVOS服务器-Xilinx ISE
io_lvds
- xilinx LVDS接口程序,xilinx LVDS接口程序-xilinx LVDS interface program,xilinx LVDS interface program
11_vga
- This vga controller write in vhdl xilinx ise Connect your vga monitor and view many color in moniotr-This is vga controller write in vhdl xilinx ise Connect your vga monitor and view many color in moniotr
BUFG_CLK0_FB_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLKDV_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
dds_easy
- 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be dir
ipcore
- XILINX公司ISE自带的IP核，功能介绍，如何使用这些IP核来加快你的开发。-IP release note guide
fft_gen
- FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho &
fpga
- fpga数字电子系统设计与开发 ISE I2C UART usb vga -ISE I2C UART usb vga
dividefreq
- Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
Leds
- Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
traffic_light
- this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit]. -this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit].
APS_M127_FPGA_ML402_Xilinx.ZIP
- Design for Xilinx ISE 11.1 For stend ML402 Acoustic position system
FPGA_RS232
- 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous ser
DesignofFloatingPointCalculatorBasedonFPGA
- 给出系统的整体框架设计和各模块的实现，包括芯片的选择、各模块之间的时序以及控制、每个运算模块详细的工作原理和算法设计流程；通过VHDL语言编程来实现浮点数的加减、乘除和开方等基本运算功能；在Xilinx ISE环境下，对系统的主要模块进行开发设计及功能仿真，验证 了基于FPGA的浮点运算。 -The overall framework of system design and realization of each module which contain selection of ch
leapyear
- 在Xilinx ISE软件下关于瑞年计数器的工程，可以判断某一年份是否为瑞年。包含代码及测试代码，已经通过编译，综合，仿真波形完全正确。-Under the Xilinx ISE software counters on the Swiss-year project, can determine whether a given year in Switzerland. Contains code and test code, has passed compiled, integrated, si
program
- 基于xilinx spantan3E开发板的20个例程 有助于需素掌握 ise和edk的使用 -Development board based on xilinx spantan3E routines help to take the 20 factors used to master ise and edk
xilinxisev6.1ikeygenror
- xilinx ise 6.1 keygen